Milestone 4

Milestone Status

This milestone is delivered.

Background

OP-TEE provides a crypto_drv abstraction for hardware-accelerated cryptographic operations, but Arm is the only architecture with an implementation currently. RISC-V RVA23 defines vector-cryptography extensions for AES and SHA-256/512, although the relevant NIST extension bundle is optional.

OP-TEE selects accelerated implementations at compile time, so this work adds a scoped RISC-V implementation using mandatory build-time constraints rather than runtime extension probing.

Milestone Description

Milestone 4 provides a RISC-V implementation of the OP-TEE crypto_drv acceleration abstraction for selected NIST algorithms using RVV 1.0 vector-cryptographic instructions.

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Milestone Update

This milestone is delivered and under upstream review.

API Function	Pull Request	Commit	Notes
import vector assembly from Linux 7.2	PR #7967	d5530e3	under review
crypto_accel_aes_expand_keys	PR #7967	d5530e3	under review
crypto_accel_aes_ecb_enc	PR #7967	fd2678e	under review
crypto_accel_aes_ecb_dec	PR #7967	fd2678e	under review
crypto_accel_aes_cbc_enc	PR #7967	fd2678e	under review
crypto_accel_aes_cbc_dec	PR #7967	fd2678e	under review
crypto_accel_aes_ctr_be_enc	PR #7967	fd2678e	under review
crypto_accel_aes_xts_enc	PR #7967	a78428a	under review
crypto_accel_aes_xts_dec	PR #7967	a78428a	under review
crypto_accel_sha256_compress	PR #7967	24e8308	under review
crypto_accel_sha512_compress	PR #7967	24e8308	under review

Test Instructions

All deliverables are pushed to RISE optee_os rp022-m4 branch and can be tested via xtest under buildroot rp022-m4 branch.

# Fetch buildroot code
$ git clone https://gitlab.com/riseproject/riscv-optee/buildroot.git -b rp022-m4

# Build the default config
# Use 'qemu_riscv64_virt_optee_llvm_defconfig' for Clang or 'qemu_riscv64_virt_optee_defconfig' for GCC
$ cd buildroot
$ make qemu_riscv64_virt_optee_llvm_defconfig

# Build all components with AES and SHA-2 enabled
$ make -j$(nproc) CMAKE_POLICY_VERSION_MINIMUM=3.5 \
      CFG_CORE_CRYPTO_AES_ACCEL=y \
      CFG_CORE_CRYPTO_SHA256_ACCEL=y \
      CFG_CORE_CRYPTO_SHA512_ACCEL=y

# Start QEMU with '-cpu rv64,zkr=on,v=true,zvkng=true,zvbb=true'
$ ./output/images/start-qemu-vector.sh

# Open a console and telnet to launch the kernel
$ telnet localhost 64320

# Run the relevant xtest after kernel login to verify AES and SHA-2
$ xtest 4001 4002 4003 4005 4017 1013

# Or just run all xtest
$ xtest

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Requirements

• Target RVA23 systems.
• Implement the NIST AES, SHA-256, and SHA-512 acceleration functions in scope.
• Integrate the RISC-V acceleration implementation into the OP-TEE build system.
• Select accelerated implementations through compile-time configuration.
• Require the necessary vector-cryptography extensions at compile time.
• Add test coverage and submit the implementation for upstream review.

The required API functions are:

1. crypto_accel_aes_expand_keys
2. crypto_accel_aes_ecb_enc
3. crypto_accel_aes_ecb_dec
4. crypto_accel_aes_cbc_enc
5. crypto_accel_aes_cbc_dec
6. crypto_accel_aes_ctr_be_enc
7. crypto_accel_aes_xts_enc
8. crypto_accel_aes_xts_dec
9. crypto_accel_sha256_compress
10. crypto_accel_sha512_compress

Scope Boundaries

• RVA22 support is excluded.
• Scalar RISC-V cryptography drivers are excluded.
• Acceleration of libtomcrypt or libmbedtls through general RVV extensions is excluded.
• Runtime probing for the optional vector-cryptography extension bundles is excluded.
• SHA-1, SHA-3, SM3, and SM4 acceleration APIs are excluded.

Deliverables

• RISC-V implementations of the ten required crypto_drv APIs.
• OP-TEE build-system integration.
• Automated coverage for the accelerated operations.
• Upstream-ready code and supporting documentation.